Ternary content addressable memory and memory cell thereof
Abstract:
A ternary content addressable memory and a memory cell thereof are provided. The ternary content addressable memory cell includes a first transistor and a second transistor. The first transistor has a gate to receive a selection signal. A first end of the first transistor is coupled to a match line. A second end of the first transistor is coupled to a source line. The second transistor has a gate to receive an inverted selection signal. A first end of the second transistor is coupled to the match line. A second end of the second transistor is coupled to the source line. The first and second transistors have charge storage structures.
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