A parallel plate capacitor structure in an integrated circuit has a first plate and a second plate separated by an insulator, such as a dielectric. Both plates are connected to an interconnect structure at a plurality of connection points. The area of the first plate that overlaps with the second plate is identified. This overlap region does not include any connection points on the first plate. For this overlap region, the lumped element model for the first plate includes nodes on the edge of the overlap region (edge nodes), and lumped resistances between the edge nodes and the node connected to the lumped capacitance. In one embodiment, the lumped element model also includes a common node, all of the edge nodes are connected to the common node by lumped resistances, and the common node is connected by a negative resistance to the lumped capacitance.