- Patent Title: Chip-stacked semiconductor package and method of manufacturing same
-
Application No.: US16749620Application Date: 2020-01-22
-
Publication No.: US11328966B2Publication Date: 2022-05-10
- Inventor: Hyoeun Kim , Yonghoe Cho , Sunkyoung Seo , Seunghoon Yeon , Sanguk Han
- Applicant: SAMSUNG ELECTRONICS CO., LTD.
- Applicant Address: KR Suwon-si
- Assignee: SAMSUNG ELECTRONICS CO., LTD.
- Current Assignee: SAMSUNG ELECTRONICS CO., LTD.
- Current Assignee Address: KR Suwon-si
- Agency: Sughrue Mion, PLLC
- Priority: KR10-2019-0075789 20190625
- Main IPC: H01L21/66
- IPC: H01L21/66 ; H01L25/065 ; H01L23/31 ; H01L25/00 ; H01L23/00 ; G01R31/28 ; G01R27/26

Abstract:
A chip-stacked semiconductor package includes a first chip including a first detection pad and a second detection pad; a second chip provided on the first chip, the second chip including a third detection pad facing the first detection pad and a fourth detection pad facing the second detection pad; and a first medium provided between the first detection pad and the third detection pad to connect the first detection pad to the third detection pad through the first medium, and a second medium, different from the first medium, provided between the second detection pad and the fourth detection pad to connect the second detection pad to the fourth detection pad through the second medium.
Information query
IPC分类: