Invention Grant
- Patent Title: DRAM with selective epitaxial transistor and buried bitline
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Application No.: US16828879Application Date: 2020-03-24
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Publication No.: US11329048B2Publication Date: 2022-05-10
- Inventor: Andrew J. Walker , Dafna Beery , Peter Cuevas , Amitay Levi
- Applicant: Integrated Silicon Solution, (Cayman) Inc.
- Applicant Address: KY Grand Cayman
- Assignee: Integrated Silicon Solution, (Cayman) Inc.
- Current Assignee: Integrated Silicon Solution, (Cayman) Inc.
- Current Assignee Address: KY Grand Cayman
- Main IPC: H01L27/108
- IPC: H01L27/108 ; H01L29/45 ; H01L29/78 ; H01L29/10 ; H01L29/66 ; H01L21/311 ; H01L21/3065 ; H01L29/423

Abstract:
A DRAM memory cell and memory cell array incorporating a metal silicide bit line buried within a doped portion of a semiconductor substrate and a vertical semiconductor structure electrically connected with a memory element such as a capacitive memory element. The buried metal silicide layer functions as a bit buried bit line which can provide a bit line voltage to the capacitive memory element via the vertical transistor structure. The buried metal silicide layer can be formed by allotaxy or mesotaxy. The vertical semiconductor structure can be formed by epitaxially growing a semiconductor material on an etched surface of the doped portion of the semiconductor substrate.
Public/Granted literature
- US20210305256A1 DRAM WITH SELECTIVE EPITAXIAL TRANSISTOR AND BURIED BITLINE Public/Granted day:2021-09-30
Information query
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