A memory transistor comprises a substrate comprising a first surface and a second surface opposing the first surface, the substrate further comprising a first trench having an opening formed in the first surface; a first dielectric layer formed on an inner surface of the first trench; a gate layer formed on the first dielectric layer in the first trench, the gate layer having a top surface lower than the first surface; and a second dielectric layer filled in the first trench and located on the top surface of the gate layer, the second dielectric layer covering the gate layer and connecting to the first dielectric layer, the second dielectric layer having a cavity formed therein.