Invention Grant
- Patent Title: Co-integration of bulk and SOI transistors
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Application No.: US16898700Application Date: 2020-06-11
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Publication No.: US11329067B2Publication Date: 2022-05-10
- Inventor: Jean-Jacques Fagot , Philippe Boivin , Franck Arnaud
- Applicant: STMicroelectronics (Crolles 2) SAS , STMicroelectronics (Rousset) SAS
- Applicant Address: FR Crolles; FR Rousset
- Assignee: STMicroelectronics (Crolles 2) SAS,STMicroelectronics (Rousset) SAS
- Current Assignee: STMicroelectronics (Crolles 2) SAS,STMicroelectronics (Rousset) SAS
- Current Assignee Address: FR Crolles; FR Rousset
- Agency: Crowe & Dunlevy
- Priority: FR1757702 20170816
- Main IPC: H01L27/12
- IPC: H01L27/12 ; H01L21/762 ; H01L29/808 ; H01L21/84 ; H01L27/06

Abstract:
An electronic integrated circuit chip includes a first transistor arranged inside and on top of a solid substrate, a second transistor arranged inside and on top of a layer of semiconductor material on insulator having a first thickness, and a third transistor arranged inside and on top of a layer of semiconductor material on insulator having a second thickness. The second thickness is greater than the first thickness. The solid substrate extends underneath the layers of semiconductor material and is insulated from those layers by the insulator.
Public/Granted literature
- US20200303423A1 CO-INTEGRATION OF BULK AND SOI TRANSISTORS Public/Granted day:2020-09-24
Information query
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