Invention Grant
- Patent Title: Parallel bit interleaver
-
Application No.: US17144275Application Date: 2021-01-08
-
Publication No.: US11329672B2Publication Date: 2022-05-10
- Inventor: Mihail Petrov
- Applicant: Panasonic Corporation
- Applicant Address: JP Osaka
- Assignee: Panasonic Corporation
- Current Assignee: Panasonic Corporation
- Current Assignee Address: JP Osaka
- Agency: Wenderoth, Lind & Ponack, L.L.P.
- Priority: EP11004126 20110518
- Main IPC: H03M13/00
- IPC: H03M13/00 ; H03M13/27 ; H03M13/11 ; H03M13/25 ; H03M13/29 ; H03M13/35 ; H04L1/00

Abstract:
A bit interleaving method involves applying a bit permutation process to a QC LDPC codeword made up of N cyclic blocks each including Q bits, and dividing the codeword, after the bit permutation process, into a plurality of constellation words each made up of M bits, the codeword being divided into N/M sections, each constellation word being associated with one of the N/M sections, and the bit permutation process being performed such that each of the constellation words includes one bit from each of M different cyclic blocks associated with a given section.
Public/Granted literature
- US20210135687A1 PARALLEL BIT INTERLEAVER Public/Granted day:2021-05-06
Information query
IPC分类: