Invention Grant
- Patent Title: Network-on-Chip topology generation
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Application No.: US17171408Application Date: 2021-02-09
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Publication No.: US11329690B2Publication Date: 2022-05-10
- Inventor: Narayana Sri Harsha Gade , Honnahuggi Harinath Venkata Naga Ambica Prasad , Anup Gangwar , Nitin Kumar Agarwal , Ravishankar Sreedharan
- Applicant: Arm Limited
- Applicant Address: GB Cambridge
- Assignee: Arm Limited
- Current Assignee: Arm Limited
- Current Assignee Address: GB Cambridge
- Agency: Leveque IP Law, P.C.
- Main IPC: H04B1/00
- IPC: H04B1/00 ; H04B1/58 ; H04L41/12 ; H04L47/125 ; H04L45/02

Abstract:
The present disclosure provides computer-based methods and a system for synthesizing a NoC that advantageously generate balanced NoC topologies without end-to-end fairness or local credit-based arbitration, and improve NoC performance when destination device bridge ports support only one incoming physical link per channel. More particularly, a clock domain is assigned to certain routers that satisfies the minimum frequency for the router while reducing clock domain transitions to neighboring routers, and the traffic flows received by these routers are balanced based on the traffic flow packet rates.
Public/Granted literature
- US20210168038A1 Network-On-Chip Topology Generation Public/Granted day:2021-06-03
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