Invention Grant
- Patent Title: Built-in self test circuit for measuring phase noise of a phase locked loop
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Application No.: US17180420Application Date: 2021-02-19
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Publication No.: US11333708B2Publication Date: 2022-05-17
- Inventor: Mao-Hsuan Chou , Ya-Tin Chang , Ruey-Bin Sheen , Chih-Hsien Chang
- Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
- Applicant Address: TW Hsin-Chu
- Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
- Current Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
- Current Assignee Address: TW Hsin-Chu
- Agency: Duane Morris LLP
- Main IPC: G01R31/317
- IPC: G01R31/317 ; H03L7/18 ; H03L7/085

Abstract:
An apparatus and method for providing a phase noise built-in self test (BIST) circuit are disclosed herein. In some embodiments, a method and apparatus for forming a multi-stage noise shaping (MASH) type high-order delta sigma (ΔΣ) time-to-digital converter (TDC) are disclosed. In some embodiments, an apparatus includes a plurality of first-order ΔΣ TDCs formed in an integrated circuit (IC) chip, wherein each of the first-order ΔΣ TDCs are connected to one another in a MASH type configuration to provide the MASH type high-order ΔΣ TDC, wherein the MASH type high-order ΔΣ TDC is configured to measure the phase noise of a device under text (DUT).
Public/Granted literature
- US20210173009A1 BUILT-IN SELF TEST CIRCUIT FOR MEASURING PHASE NOISE OF A PHASE LOCKED LOOP Public/Granted day:2021-06-10
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