A circuit for a bus system is provided. The circuit includes: an ascertainment circuit, which is configured to ascertain a first state in which an absolute difference of a voltage between two bus-side terminals is above a threshold value, to ascertain a second state in which the absolute value of the voltage between the two bus-side terminals is below the threshold value, to ascertain a bit boundary as a function of a number of state transitions between the first and second state, and to ascertain at least one time window, the start of which is situated before the bit boundary and the end of which is situated after the bit boundary; and a suppression circuit, which is configured to be activated when a state transition from the first state into the second state occurs within the ascertained time window.