Invention Grant
- Patent Title: Method of manufacturing a semiconductor device and a semiconductor device
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Application No.: US16426552Application Date: 2019-05-30
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Publication No.: US11335604B2Publication Date: 2022-05-17
- Inventor: Chao-Ching Cheng , I-Sheng Chen , Hung-Li Chiang , Tzu-Chiang Chen , Kai-Tai Chang
- Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
- Applicant Address: TW Hsinchu
- Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
- Current Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
- Current Assignee Address: TW Hsinchu
- Agency: McDermott Will & Emery LLP
- Main IPC: H01L21/8238
- IPC: H01L21/8238 ; H01L29/78 ; H01L27/092 ; H01L29/165 ; H01L29/66 ; H01L21/306 ; H01L29/06 ; H01L21/02

Abstract:
In a method of manufacturing a semiconductor device, a fin structure having a lower fin structure and an upper fin structure disposed over the lower fin structure is formed. The upper fin structure includes first semiconductor layers and second semiconductor layers alternately stacked. The first semiconductor layers are partially etched to reduce widths of the first semiconductor layers. An oxide layer is formed over the upper fin structure. A sacrificial gate structure is formed over the upper fin structure with the oxide layer. A source/drain epitaxial layer is formed over a source/drain region of the fin structure. The sacrificial gate structure is removed to form a gate space. The oxide layer is removed to expose the second semiconductor layers in the gate space. A gate structure is formed around the second semiconductor layers in the gate space.
Information query
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