Invention Grant
- Patent Title: Fast-lane routing for multi-chip packages
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Application No.: US16106926Application Date: 2018-08-21
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Publication No.: US11336559B2Publication Date: 2022-05-17
- Inventor: Adel A. Elsherbini , Tejpal Singh , Shawna M. Liff , Gerald S. Pasdast , Johanna M. Swan
- Applicant: Intel Corporation
- Applicant Address: US CA Santa Clara
- Assignee: Intel Corporation
- Current Assignee: Intel Corporation
- Current Assignee Address: US CA Santa Clara
- Agency: Patent Capital Group
- Main IPC: H04L45/122
- IPC: H04L45/122 ; H04L45/12 ; H04L9/40 ; G06F12/0842 ; H04L49/109

Abstract:
Embodiments herein may relate to a processor package with a substrate and a multi-chip processor coupled with the substrate. The multi-chip processor may include a dual-sided interconnect structure coupled with a first chip, a second chip, and a third chip. The first chip may be communicatively coupled with the second chip by an on-chip communication route. Likewise, the second chip may be communicatively coupled with the first chip by an on-chip communication route. Additionally, the first chip may be communicatively coupled with the third chip by a fast-lane communication route. Other embodiments may be described and/or claimed.
Public/Granted literature
- US20200067816A1 FAST-LANE ROUTING FOR MULTI-CHIP PACKAGES Public/Granted day:2020-02-27
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