Invention Grant
- Patent Title: Testing holders for chip unit and die package
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Application No.: US16912017Application Date: 2020-06-25
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Publication No.: US11340291B2Publication Date: 2022-05-24
- Inventor: Mill-Jer Wang , Kuo-Chuan Liu , Ching-Nen Peng , Hung-Chih Lin , Hao Chen
- Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
- Applicant Address: TW Hsinchu
- Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
- Current Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
- Current Assignee Address: TW Hsinchu
- Agency: McDermott Will & Emery LLP
- Main IPC: G01R31/28
- IPC: G01R31/28 ; G01R31/3185 ; G01R1/04 ; G01R1/067

Abstract:
A testing holder for a chip unit, a multi site holding frame for plural chip units and a method for testing a die thereof are provided. The proposed multi site holding frame for testing plural chip units simultaneously includes a first holder frame having a plurality of testing holders. Each of the plurality of testing holders includes a holder body containing a specific one of the plural chip units, and a pressure releasing device formed on the holder body to release an insertion pressure when the specific one of the plural chip units is inserted in the holder body.
Public/Granted literature
- US20200326370A1 TESTING HOLDERS FOR CHIP UNIT AND DIE PACKAGE Public/Granted day:2020-10-15
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