A memory system includes a semiconductor memory device and a controller. The semiconductor memory device includes a plurality of planes and performs a protection operation and a general operation on the plurality of planes. The controller controls an operation of the semiconductor memory device by transferring a Sudden Power Off (SPO) process command, which is generated in response to a Sudden Power Off (SPO) that occurs in the memory system, to the semiconductor memory device. The semiconductor memory device is configured to interrupt the general operations among operations performed on the plurality of planes in response to the SPO process command.