A level shifter circuit includes an input terminal, a first output terminal, a second output terminal, an output stage, a first control bias unit, a second control bias unit, and an output stage. The input stage includes a first transistor and a second transistor, and their gates are coupled to the input terminal. The first control bias unit includes a third transistor and a fourth transistor coupled to the first transistor and second transistor respectively and their gates are controlled by a first bias. The output stage includes a fifth transistor and a sixth transistor coupled to the third transistor and fourth transistor respectively and their gates are coupled to the first output terminal and second output terminal. The second control bias unit includes a seventh transistor and an eighth transistor coupled to the fifth transistor and sixth transistor respectively and their gates are controlled by a second bias.