Invention Grant
- Patent Title: System and method for prioritization of bit error correction attempts
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Application No.: US16588089Application Date: 2019-09-30
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Publication No.: US11342044B2Publication Date: 2022-05-24
- Inventor: Ziv Hershman , Ilan Margalit , Avraham Fishman
- Applicant: NUVOTON TECHNOLOGY CORPORATION
- Applicant Address: TW Hsinchu Science Park
- Assignee: NUVOTON TECHNOLOGY CORPORATION
- Current Assignee: NUVOTON TECHNOLOGY CORPORATION
- Current Assignee Address: TW Hsinchu Science Park
- Agency: Oliff PLC
- Main IPC: G06F21/00
- IPC: G06F21/00 ; G11C29/52 ; G11C29/50 ; G11C29/44 ; G11C29/34 ; G11C29/42

Abstract:
System, method and computer program product for prioritizing trial-and-error attempted corrections of bit/s, in a memory, in which logical bit levels are determined by thresholding voltage values using threshold/s, the method comprising ranking bits such that a first bit is ranked before a second bit, which is less likely than said first bit to be erroneous and sequentially attempting to correct the bits in order of the ranking, including attempting to correct the first bit before attempting to correct the second bit.
Public/Granted literature
- US20200381076A1 SYSTEM AND METHOD FOR PRIORITIZATION OF BIT ERROR CORRECTION ATTEMPTS Public/Granted day:2020-12-03
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