- Patent Title: Synchronization of clock signals generated using output dividers
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Application No.: US17186180Application Date: 2021-02-26
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Publication No.: US11342926B2Publication Date: 2022-05-24
- Inventor: James D. Barnette , William Anker , Xue-Mei Gong
- Applicant: Silicon Laboratories Inc.
- Applicant Address: US TX Austin
- Assignee: Silicon Laboratories Inc.
- Current Assignee: Silicon Laboratories Inc.
- Current Assignee Address: US TX Austin
- Agency: Zagorin Cave LLP
- Main IPC: H03L7/099
- IPC: H03L7/099 ; H03L7/087

Abstract:
A method for operating a clock product includes selectively coupling a first output divider and a second output divider based on a determination of whether the first divider value is integrally related to the second divider value. In response to the first divider value being integrally related to the second divider value, the selectively coupling includes cascading the first output divider with the second output divider. In in response to the first divider value being non-integrally related to the second divider value, the selectively coupling includes configuring the second output divider to be cascaded with a first phase-locked loop and in parallel with the first output divider and to be responsive to an error correction signal based on a difference in response times of the first output divider and the second output divider to a change in a filtered phase difference signal of the first phase-locked loop.
Public/Granted literature
- US20210184687A1 SYNCHRONIZATION OF CLOCK SIGNALS GENERATED USING OUTPUT DIVIDERS Public/Granted day:2021-06-17
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