A packet processing apparatus sets, for each TS as a gate state of each of a first gate and a second gate, a priority state, a normal state, and a mixed state and sets a predetermined TS associated with a cyclic pattern of the first packet to the priority or the mixed state. The apparatus allocates, when an amount of output delay of the first packet that is in the mixed state in the predetermined TS is within an allowable amount, the first packet and the second packet to the predetermined TS. The apparatus sets output timing of the first packet allocated in the predetermined TS to the priority state and sets output timing of the second packet allocated in the predetermined TS to the normal state.