Invention Grant
- Patent Title: Dual metal via for contact resistance reduction
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Application No.: US16870360Application Date: 2020-05-08
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Publication No.: US11349015B2Publication Date: 2022-05-31
- Inventor: Chung-Liang Cheng , Yen-Yu Chen
- Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
- Applicant Address: TW Hsin-Chu
- Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
- Current Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
- Current Assignee Address: TW Hsin-Chu
- Agency: Haynes and Boone, LLP
- Main IPC: H01L29/66
- IPC: H01L29/66 ; H01L29/78 ; H01L29/06 ; H01L29/423 ; H01L21/762 ; H01L21/285 ; H01L21/768

Abstract:
A semiconductor device includes a conductive feature over a substrate, a ruthenium-containing feature disposed over the conductive feature, and a first barrier layer disposed over the conductive feature and over sidewalls of the ruthenium-containing feature. The semiconductor device also includes a second barrier layer disposed over sidewalls of the first barrier layer, and a third barrier layer disposed over sidewalls of the second barrier layer. The first, second, and third barrier layers include different material compositions.
Public/Granted literature
- US20200273966A1 Dual Metal Via for Contact Resistance Reduction Public/Granted day:2020-08-27
Information query
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