A flip-flop circuit includes gate circuits of which the number is N being an integer of 3 or more, and in which an output signal from the (N−1)th gate circuit is used as an input signal of the N-th gate circuit, the gate circuit being configured to output the output signal in response to a clock signal and the input signal. The N gate circuits include a first MOS transistor group including MOS transistors which are in an OFF state when a potential of an output signal node that outputs the output signal is held, and a second MOS transistor group including MOS transistors which are in an ON state when the potential of the output signal node is held. A threshold voltage of at least one MOS transistor in the first MOS transistor group is higher than a threshold voltage of at least one MOS transistor in the second MOS transistor group.