Invention Grant
- Patent Title: High-side gate over-voltage stress testing
-
Application No.: US16792671Application Date: 2020-02-17
-
Publication No.: US11353494B2Publication Date: 2022-06-07
- Inventor: Sigfredo E. Gonzalez Diaz , Benjamin Lee Amey , Patrick Michael Teterud , Hung Nguyen
- Applicant: Texas Instruments Incorporated
- Applicant Address: US TX Dallas
- Assignee: Texas Instruments Incorporated
- Current Assignee: Texas Instruments Incorporated
- Current Assignee Address: US TX Dallas
- Agent Valerie M. Davis; Charles A. Brill; Frank D. Cimino
- Main IPC: G01R31/26
- IPC: G01R31/26

Abstract:
A testing system includes: a substrate having a probe pad and having a supply input; driver circuitry having a driver output; a transistor having a gate, a source, and a drain; and a field effect transistor (FET) engager. The gate of the transistor is coupled to the driver output, and the drain of the transistor is coupled to the supply input. The FET engager is configured to couple the probe pad to the gate of the transistor and provide test instrument measurement of gate current of the transistor without test instrument probe capacitance impacting operation of the transistor.
Public/Granted literature
- US20200182925A1 HIGH-SIDE GATE OVER-VOLTAGE STRESS TESTING Public/Granted day:2020-06-11
Information query