Pixel structure and pixel control method, array substrate and display device
Abstract:
A pixel structure includes a first sub-pixel that includes a first thin film transistor (T1), a first common electrode (C1), and a first pixel electrode (Pix1) that is coupled to the first thin film transistor (T1); a second sub-pixel that includes a second thin film transistor (T2), a second common electrode (C2), and a second pixel electrode (Pix2) that is coupled to the second thin film transistor (T2); a discharge device that includes a control terminal, an input terminal, and an output terminal; and a gate line (GATE). The first thin film transistor (T1), the second thin film transistor (T2), and the control terminal of the discharge device are coupled to the gate line (GATE).
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