Invention Grant
- Patent Title: Read latency reduction through command and polling overhead avoidance
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Application No.: US16899923Application Date: 2020-06-12
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Publication No.: US11354041B2Publication Date: 2022-06-07
- Inventor: Todd Lindberg , Robert Ellis , Kevin O'Toole
- Applicant: WESTERN DIGITAL TECHNOLOGIES, INC.
- Applicant Address: US CA San Jose
- Assignee: WESTERN DIGITAL TECHNOLOGIES, INC.
- Current Assignee: WESTERN DIGITAL TECHNOLOGIES, INC.
- Current Assignee Address: US CA San Jose
- Agency: ArentFox Schiff LLP
- Main IPC: G06F13/16
- IPC: G06F13/16 ; G06F3/06

Abstract:
Aspects of a storage device including a memory and a controller are provided which allow for reduction of latency and improve QoS for reads performed in memory locations such as multi-plane dies sharing a bus with the controller. When the controller receives a host read command, the controller sends a read sense command to a memory location to perform a read operation. The controller also sends a status polling command to the memory location to check die status. While the read operation is being performed, and while other read operations are being performed in other memory locations, the controller refrains from polling this memory location and the other memory locations for die status. Rather, the controller continuously toggles a read enable input to the memory location until the read operation is complete and the die status is ready, after which the controller receives data from the memory location.
Public/Granted literature
- US20210389878A1 Read Latency Reduction through Command and Polling Overhead Avoidance Public/Granted day:2021-12-16
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