The present disclosure provides a compressor circuit, a Wallace tree circuit, a multiplier circuit, a chip and an apparatus. The compressor circuit includes a first full adder, a second full adder, and a first selection circuit. An output end of the first full adder is connected to an input end of the first selection circuit, and an output end of the first selection circuit is connected to an input end of the second full adder. The first selection circuit is configured to determine an input signal output by the first selection circuit to the second full adder according to a first selection signal; and the input signal output by the first selection circuit to the second full adder and a most significant bit signal of a plurality of input signals of the compressor circuit are used to control turning on and turning off of the second full adder, which can reduce circuit power consumption and delay.