A chip system including I/O pins, a memory chip and a processing chip is provided. The processing chip includes I/O pads, memory access pads, a processor, an I/O controller, a memory controller and a transmission gate module. Under an operation mode, the I/O controller allows the processor to communicate with an external circuit device through the I/O controller, the I/O pads and the I/O pins. Under the operation mode, the memory controller allows the processor to access the memory chip through the memory controller and the memory access pads. The transmission gate module is enabled during a program mode or a test mode to allow the external circuit device to perform programming or testing on the memory chip through the I/O pins, the I/O pads, the transmission gate module and the memory access pads.