Invention Grant
- Patent Title: Hang correction in a power management interface bus
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Application No.: US16997542Application Date: 2020-08-19
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Publication No.: US11354266B2Publication Date: 2022-06-07
- Inventor: Sharon Graif , Kishalay Haldar , Navdeep Mer , Viney Kumar , Sriharsha Chakka
- Applicant: QUALCOMM Incorporated
- Applicant Address: US CA San Diego
- Assignee: QUALCOMM Incorporated
- Current Assignee: QUALCOMM Incorporated
- Current Assignee Address: US CA San Diego
- Agency: Qualcomm Incorporated
- Main IPC: G06F13/42
- IPC: G06F13/42 ; G06F13/40 ; G06F13/374

Abstract:
The systems and methods for hang correction in a power management interface bus cause secondary master devices associated with the power management interface bus to utilize timers to determine if a master that won arbitration has asserted a clock signal within a predefined amount of time. If a timer for a secondary master device expires without a clock signal being asserted by the winning master, the secondary master will assume ownership of the bus and assert a clock signal. Priorities between secondary masters are created by using a master identification (MID) value assigned during bus enumeration to determine a timer value. By allowing the secondary masters to assume ownership after expiration of respective timers, bus ownership is maintained in the event that a winning master hangs and does not assert ownership.
Public/Granted literature
- US20220058154A1 HANG CORRECTION IN A POWER MANAGEMENT INTERFACE BUS Public/Granted day:2022-02-24
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