A memory device, and a method of operating the memory device, includes a memory block configured to include a plurality of memory cells that are stacked to be spaced apart from each other on a substrate and to include word lines coupled to the plurality of memory cells, and bit lines and a source line coupled to both ends of strings including the plurality of memory cells, and peripheral circuits configured to perform an erase operation on the memory block, wherein the peripheral circuits are configured to perform the erase operation on the plurality of memory cells included in the memory block, and thereafter perform a defect detection operation on memory cells selected from among the plurality of memory cells depending on sizes of the plurality of memory cells.