Invention Grant
- Patent Title: Integrated circuit in hybrid row height structure
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Application No.: US16882103Application Date: 2020-05-22
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Publication No.: US11355395B2Publication Date: 2022-06-07
- Inventor: Jerry Chang-Jui Kao , Hui-Zhong Zhuang , Li-Chung Hsu , Sung-Yen Yeh , Yung-Chen Chien , Jung-Chan Yang , Tzu-Ying Lin
- Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
- Applicant Address: TW Hsinchu
- Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
- Current Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
- Current Assignee Address: TW Hsinchu
- Agency: Maschoff Brennan
- Main IPC: H01L21/822
- IPC: H01L21/822 ; H01L23/535 ; H01L23/50 ; H01L21/48
Abstract:
A semiconductor device includes several first cell rows extending in a first direction, each of the first cell rows having a first row height; several second cell rows extending in the first direction, each of the second cell rows having a second row height smaller than the first row height, wherein the first cell rows and the second cell rows are interlaced; a first cell arranged in a first row of the first cell rows; and at least one second cell arranged in at least one row of the second cell rows, wherein the at least one second cell abuts the first cell in a second direction different from the first direction, wherein the at least one second cell and at least one circuit component included in the first cell have the same operation configuration.
Public/Granted literature
- US20210366774A1 INTEGRATED CIRCUIT Public/Granted day:2021-11-25
Information query
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