An integrated circuit includes a bias pad within a buried oxide layer. A layer of semiconductor material is over the buried oxide layer. The layer of semiconductor material includes a doped regions for a transistor. An inter layer dielectric (ILD) material covers the layer of semiconductor material and a gate electrode for the transistor. The integrated circuit includes one or more bias contacts extending through the ILD material within an isolation region in the layer of semiconductor material. Bias contacts electrically connect to the first bias pad. The isolation structure insulates the one or more bias contacts from the doped regions of the transistor within the layer of semiconductor material. The one or more bias contacts are electrically connected to an interconnection structure of the integrated circuit which is configured to connect a voltage source to the bias pad.