- Patent Title: Folded channel vertical transistor and method of fabricating same
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Application No.: US16525015Application Date: 2019-07-29
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Publication No.: US11355632B2Publication Date: 2022-06-07
- Inventor: Qing Liu
- Applicant: Avago Technologies International Sales Pte. Limited
- Applicant Address: SG Singapore
- Assignee: Avago Technologies International Sales Pte. Limited
- Current Assignee: Avago Technologies International Sales Pte. Limited
- Current Assignee Address: SG Singapore
- Agency: Foley & Lardner LLP
- Main IPC: H01L29/78
- IPC: H01L29/78 ; H01L21/762 ; H01L29/66

Abstract:
A semiconductor structure includes a substrate having a top surface, pillar structures formed on top of the substrate, a gate conductor, a drain/source region and a source/drain region. Each pillar structure of the pillar structures includes a first end and a second end, and the first end is closer to the substrate than the second end. The gate conductor surrounds each of the pillar structures disposed between the first end and the second end. The drain/source region is at the top surface of the substrate and in contact with the first end of a first pillar structure of the pillar structures, and the source/drain region is at the top surface of the substrate and in contact with the first end of a second pillar structure of the pillar structures.
Public/Granted literature
- US20210036151A1 FOLDED CHANNEL VERTICAL TRANSISTOR AND METHOD OF FABRICATING SAME Public/Granted day:2021-02-04
Information query
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