A circuit comprising a frequency to voltage converter having an input configured to receive a signal and an output coupled to a first node and another frequency to voltage converter having an input configured to receive a reference clock and an output coupled to a second node. The circuit also comprises a voltage source coupled between the first node and a third node, a voltage source coupled between the second node and a fourth node, a switch coupled between the first node and the third node, and a switch coupled between the second and fourth nodes. The circuit further comprises a comparator having an input coupled to the second node, another input coupled to the third node, and an output, a logic circuit having an input coupled to the comparator output and an output, and a counter having an input coupled to the logic circuit output and an output.