A self-test verification device may include one or more first processors, configured to generate an instruction for one or more second processors to perform one or more device self-tests; determine for a received result of the one or more device self-tests, whether the result fulfills a predetermined receive time criterion describing an acceptable time until the result should have been received; determine a difference between the received result and a target result; and if the predefined receive time criterion is fulfilled and if the difference between the received result and the target result is within a predetermined range, generate a signal representing a passed self-test.