Invention Grant
- Patent Title: Fault tolerant data coherence in large-scale distributed cache systems
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Application No.: US16697019Application Date: 2019-11-26
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Publication No.: US11360899B2Publication Date: 2022-06-14
- Inventor: Marjan Radi , Dejan Vucinic
- Applicant: Western Digital Technologies, Inc.
- Applicant Address: US CA San Jose
- Assignee: Western Digital Technologies, Inc.
- Current Assignee: Western Digital Technologies, Inc.
- Current Assignee Address: US CA San Jose
- Agency: Barry IP Law, P.C.
- Main IPC: G06F12/0862
- IPC: G06F12/0862 ; G06F12/0817 ; G06F12/0802 ; G06F12/0806 ; H04L67/1097 ; H04L67/568 ; G06F9/34 ; G06F9/38

Abstract:
A programmable switch includes a plurality of ports for communication with devices on a network. Circuitry of the programmable switch is configured to receive a cache line request from a client on the network to obtain a cache line for performing an operation by the client. A port is identified for communicating with a memory device storing the cache line. The memory device is one of a plurality of memory devices used for a distributed cache. The circuitry is further configured to update a cache directory for the distributed cache based on the cache line request, and send the cache line request to the memory device using the identified port. In one aspect, it is determined whether the cache line request is for modifying the cache line.
Public/Granted literature
- US20200351370A1 FAULT TOLERANT DATA COHERENCE IN LARGE-SCALE DISTRIBUTED CACHE SYSTEMS Public/Granted day:2020-11-05
Information query
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