A system includes a memory system and a processor of a first processing system including a processor core, a direct memory access controller, and a communication interface. The processor core is configured to execute a plurality of instructions to configure the direct memory access controller to trigger a transmitter interrupt upon transmitting a first synchronization message through the communication interface to a second processing system, configure the direct memory access controller to trigger a receiver interrupt upon receiving a second synchronization message from the second processing system, determine a time difference between triggering of the transmitter interrupt and the receiver interrupt, and adjust a synchronization skew of a real-time scheduler based on the time difference to tune real-time synchronization between the first processing system and the second processing system.