Invention Grant
- Patent Title: Semiconductor chip stack arrangement and semiconductor chip for producing such a semiconductor chip stack arrangement
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Application No.: US15734772Application Date: 2018-06-05
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Publication No.: US11367709B2Publication Date: 2022-06-21
- Inventor: Matthias Fettke , Andrej Kolbasow
- Applicant: PAC TECH—PACKAGING TECHNOLOGIES GMBH
- Applicant Address: DE Nauen
- Assignee: PAC TECH—PACKAGING TECHNOLOGIES GMBH
- Current Assignee: PAC TECH—PACKAGING TECHNOLOGIES GMBH
- Current Assignee Address: DE Nauen
- Agency: Quarles & Brady LLP
- International Application: PCT/EP2018/064783 WO 20180605
- International Announcement: WO2019/233568 WO 20191212
- Main IPC: H01L25/065
- IPC: H01L25/065 ; H01L23/36 ; H01L23/498 ; H01L23/00

Abstract:
A semiconductor-chip stack package includes a plurality of semiconductor chips disposed in a stack arrangement and at least one connecting substrate which connects the semiconductor chips. The semiconductor chips include a chip terminal face on a chip edge extending at least partially as a side terminal face in a side surface of the semiconductor chip. The side surfaces of the semiconductor chips provided with the side terminal face are arranged in a shared side surface plane S of the semiconductor-chip stack arrangement. The connecting substrate is arranged with a contact surface parallel to the side surface plane S of the semiconductor chips. Substrate terminal faces are formed on the contact surface for connecting a connection conductor structure formed in the connecting substrate and which are connected to the side terminal faces via a connecting material in a connection plane V1 parallel to the contact surface.
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Information query
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