- Patent Title: Integrated circuits with stacked transistors and methods of manufacturing the same using processes which fabricate lower gate structures following completion of portions of an upper transistor
-
Application No.: US16650795Application Date: 2017-12-27
-
Publication No.: US11374024B2Publication Date: 2022-06-28
- Inventor: Aaron D. Lilak , Rishabh Mehandru , Gilbert Dewey , Willy Rachmady , Anh Phan
- Applicant: Intel Corporation
- Applicant Address: US CA Santa Clara
- Assignee: Intel Corporation
- Current Assignee: Intel Corporation
- Current Assignee Address: US CA Santa Clara
- Agency: Essential Patents Group, LLP
- International Application: PCT/US2017/068565 WO 20171227
- International Announcement: WO2019/132893 WO 20190704
- Main IPC: H01L27/12
- IPC: H01L27/12 ; H01L21/822 ; H01L21/8234 ; H01L25/065 ; H01L27/06 ; H01L29/78
Abstract:
Integrated circuits with stacked transistors and methods of manufacturing the same are disclosed. An example integrated circuit includes a first transistor in a first portion of the integrated circuit, and a second transistor stacked above the first transistor and in a second portion of the integrated circuit above the first portion. The integrated circuit further includes a bonding layer between the first and second vertical portions of the integrated circuit. The bonding layer includes an opening extending therethrough between the first and second vertical portions of the integrated circuit. The integrated circuit also includes a gate dielectric on an inner wall of the opening.
Public/Granted literature
Information query
IPC分类:
