Invention Grant
- Patent Title: Arithmetic logic unit layout for a processor
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Application No.: US16540602Application Date: 2019-08-14
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Publication No.: US11379406B2Publication Date: 2022-07-05
- Inventor: Radoslav Danilak
- Applicant: TACHYUM LTD.
- Applicant Address: US CA San Jose
- Assignee: TACHYUM LTD.
- Current Assignee: TACHYUM LTD.
- Current Assignee Address: US CA San Jose
- Agency: Polsinelli PC
- Main IPC: G06F15/78
- IPC: G06F15/78 ; G06F9/38 ; G06F7/57 ; G06F9/30 ; G06F16/901 ; G06F8/41
Abstract:
A processor has first, second and third ALUs. The first ALU has on a first side an input and an output. The second ALU has a first side facing the first side of the first ALU, an input and an output on the first side of the second ALU and being in a rotated orientation relative to the input and the output of the first side of the first ALU, and an output on a second side of the second ALU. The third ALU has a first side facing the second side of the second ALU, and an input and an output on the first side of the third ALU. The input of the first side of the first ALU is logically directly connected to the output of the first side of the second ALU.
Public/Granted literature
- US20200057748A1 ARITHMETIC LOGIC UNIT LAYOUT FOR A PROCESSOR Public/Granted day:2020-02-20
Information query
