Invention Grant
- Patent Title: Method and process using dual memorization layer for multi-color spacer patterning
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Application No.: US16864472Application Date: 2020-05-01
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Publication No.: US11380579B2Publication Date: 2022-07-05
- Inventor: Hirokazu Aizawa , Kaoru Maekawa , Akiteru Ko
- Applicant: Tokyo Electron Limited
- Applicant Address: JP Tokyo
- Assignee: Tokyo Electron Limited
- Current Assignee: Tokyo Electron Limited
- Current Assignee Address: JP Tokyo
- Main IPC: H01L21/768
- IPC: H01L21/768 ; H01L23/532

Abstract:
A self-aligned multiple patterning (SAMP) multi-color spacer patterning process is disclosed for formation of structures on substrates. Trenches and vias may be formed in the process. A trench memorization layer and a via memorization layer may be formed on the substrate. In one embodiment, the trench memorization layer and the via memorization layer are formed between the multi-color spacer patterning structures and a low-k interlayer dielectric layer. The use of the trench memorization layer and the via memorization layer allows the formation of trenches and vias in the low-k interlayer dielectric layer without causing damage to the low-k properties of the low-k interlayer dielectric layer.
Public/Granted literature
- US20210343586A1 Method and Process Using Dual Memorization Layer for Multi-Color Spacer Patterning Public/Granted day:2021-11-04
Information query
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