Invention Grant
- Patent Title: CMOS over array of 3-D DRAM device
-
Application No.: US17230591Application Date: 2021-04-14
-
Publication No.: US11380691B1Publication Date: 2022-07-05
- Inventor: Sony Varghese , Fred Fishburn
- Applicant: Applied Materials, Inc.
- Applicant Address: US CA Santa Clara
- Assignee: Applied Materials, Inc.
- Current Assignee: Applied Materials, Inc.
- Current Assignee Address: US CA Santa Clara
- Agency: KDB Firm PLLC
- Main IPC: H01L27/108
- IPC: H01L27/108

Abstract:
Disclosed are 3-D DRAM devices and methods of forming 3-D DRAM devices. One method may include forming a stack of DRAM device layers, forming a MOS substrate directly atop the stack of alternating DRAM device layers, and forming a trench through the MOS substrate and the stack of DRAM device layers. The method may further include depositing a protection layer over the MOS substrate, wherein the protection layer is deposited at a non-zero angle of inclination relative to a vertical extending from a top surface of the MOS substrate.
Information query
IPC分类: