Invention Grant
- Patent Title: Memory with optimized resistive layers
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Application No.: US16941885Application Date: 2020-07-29
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Publication No.: US11380732B2Publication Date: 2022-07-05
- Inventor: Lei Wei , Pengyuan Zheng , Kevin Lee Baker , Efe Sinan Ege , Adam Thomas Barton , Rajasekhar Venigalla
- Applicant: Micron Technology, Inc.
- Applicant Address: US ID Boise
- Assignee: Micron Technology, Inc.
- Current Assignee: Micron Technology, Inc.
- Current Assignee Address: US ID Boise
- Agency: Holland & Hart LLP
- Main IPC: H01L27/24
- IPC: H01L27/24 ; H01L45/00

Abstract:
A memory system may include separate amounts or types of resistive material that may be deposited over memory cells and conductive vias using separate resistive layers in the access lines. A first resistive material layer may be deposited over the memory cells prior to performing an array termination etch used to deposit the conductive via. The array termination etch may remove the first resistive material over the portion of the array used to deposit the conductive via. A second resistive material layer may be deposited after the etch has occurred and the conductive via has been formed. The second resistive material layer may be deposited over the conductive via.
Public/Granted literature
- US20220037403A1 MEMORY WITH OPTIMIZED RESISTIVE LAYERS Public/Granted day:2022-02-03
Information query
IPC分类: