Invention Grant
- Patent Title: High throughput and area efficient partial parallel hard decoder for low-density parity-check codes
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Application No.: US17198463Application Date: 2021-03-11
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Publication No.: US11381254B1Publication Date: 2022-07-05
- Inventor: Shriharsha Koila
- Applicant: Smart IOPS, Inc.
- Applicant Address: US CA Milpitas
- Assignee: Smart IOPS, Inc.
- Current Assignee: Smart IOPS, Inc.
- Current Assignee Address: US CA Milpitas
- Agency: Chip Law Group
- Main IPC: H03M13/00
- IPC: H03M13/00 ; H03M13/11 ; H03M13/25

Abstract:
A hard decoder includes an input data handler that receives and rearranges a low-density parity-check (LDPC) codeword, and a variable node updater that iteratively updates the rearranged LDPC codeword to generate an updated LDPC codeword during each decoding iteration of the rearranged LDPC codeword. The hard decoder further includes a syndrome generator that generates a syndrome vector associated with the updated LDPC codeword of each decoding iteration. During each decoding iteration, the rearranged LDPC codeword is updated based on a threshold value and the syndrome vector associated with the updated LDPC codeword of a previous decoding iteration and a validity of the updated LDPC codeword of the previous decoding iteration. The hard decoder further includes an output data handler that extracts a message from the updated LDPC codeword that is valid and outputs the extracted message.
Information query
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