An image processing device includes an interface and a control circuit. The interface is configured to receive input line signals in synchronization with input horizontal synchronization signals, respectively. The control circuit is configured to store line image data contained in each of input line signals in the order of reception, generate internal horizontal synchronization signals, and output internal line signals containing the line image data in the input line signals, in synchronization with the internal horizontal synchronization signals, respectively. The input line signals include a first input line signal containing first line image data, and the internal line signals include a first internal line signal containing the first line image data. A horizontal cycle of the internal horizontal synchronization signal corresponding to the first internal line signal is less than a horizontal cycle of the input horizontal synchronization signal corresponding to the first input line signal.