Invention Grant
- Patent Title: Multiple independent synchonization named barrier within a thread group
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Application No.: US16798603Application Date: 2020-02-24
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Publication No.: US11409579B2Publication Date: 2022-08-09
- Inventor: James Valerio , Vasanth Ranganathan , Joydeep Ray
- Applicant: Intel Corporation
- Applicant Address: US CA Santa Clara
- Assignee: Intel Corporation
- Current Assignee: Intel Corporation
- Current Assignee Address: US CA Santa Clara
- Agency: Jaffery Watson Mendonsa & Hamilton LLP
- Main IPC: G06F9/52
- IPC: G06F9/52 ; G06F9/54 ; G06F9/30 ; G06F9/38 ; G06F9/48 ; G06T1/20 ; G06F15/78 ; G06N20/00

Abstract:
An apparatus to facilitate thread barrier synchronization is disclosed. The apparatus includes a plurality of processing resources to execute a plurality of execution threads included in a thread workgroup and barrier synchronization hardware to assign a first named barrier to a first set of the plurality of execution threads in the thread workgroup, assign a second named barrier to a second set of the plurality of execution threads in the thread workgroup, synchronize execution of the first set of execution threads via the first named barrier and synchronize execution of the second set of execution threads via the second named barrier.
Public/Granted literature
- US20210263785A1 BARRIER SYNCHRONIZATION MECHANISM Public/Granted day:2021-08-26
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