Microelectronic device testing, and related methods, devices, and systems, are described herein. A device may include a memory array including a number of rows and a number of columns. The memory device may further include circuitry coupled to the memory array. The circuitry may be configured to perform a testing operation on each row of the number of rows to detect: a first fail of a first row of the number of rows; and a set of additional fails associated with a set of rows of the number of rows. The circuitry may also be configured to determine whether the set of rows is adjacent the first row. Further, in response to determining that the set of rows is adjacent the first row, the circuitry may be configured to generate a signal indicative of a failure of a column of the number of columns.