Invention Grant
- Patent Title: Subtractive back-end-of-line vias
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Application No.: US16841994Application Date: 2020-04-07
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Publication No.: US11410879B2Publication Date: 2022-08-09
- Inventor: Chanro Park , Koichi Motoyama , Kenneth Chun Kuen Cheng , Chih-Chao Yang
- Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
- Applicant Address: US NY Armonk
- Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
- Current Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
- Current Assignee Address: US NY Armonk
- Agency: Tutunjian & Bitetto, P.C.
- Agent L. Jeffrey Kelly
- Main IPC: H01L21/768
- IPC: H01L21/768 ; H01L23/522 ; H01L23/532 ; H01L23/535

Abstract:
Integrated chips and methods of forming the same include forming a conductive layer over a lower conductive line. The conductive layer is etched to form a via on the lower conductive line. A first insulating layer is formed around the via. The first insulating layer is etched back to a height below a height of the via. An upper conductive line is formed on the via, making contact with at least a top surface and a side surface of the via.
Public/Granted literature
- US20210313226A1 SUBTRACTIVE BACK-END-OF-LINE VIAS Public/Granted day:2021-10-07
Information query
IPC分类: