Invention Grant
- Patent Title: Chip package structure with bump
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Application No.: US17106941Application Date: 2020-11-30
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Publication No.: US11410956B2Publication Date: 2022-08-09
- Inventor: Wei-Yu Chen , Li-Hsien Huang , An-Jhih Su , Hsien-Wei Chen
- Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
- Applicant Address: TW Hsinchu
- Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
- Current Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
- Current Assignee Address: TW Hsinchu
- Agency: Slater Matsil, LLP
- Main IPC: H01L23/00
- IPC: H01L23/00 ; H01L23/31 ; H01L25/065 ; H01L23/498 ; H01L21/56 ; H01L25/00 ; H01L21/48 ; H01L21/54

Abstract:
A chip package structure is provided. The chip package structure includes a redistribution structure and a first chip structure over the redistribution structure. The chip package structure also includes a first solder bump between the redistribution structure and the first chip structure and a first molding layer surrounding the first chip structure. The chip package structure further includes a second chip structure over the first chip structure and a second molding layer surrounding the second chip structure. In addition, the chip package structure includes a third molding layer surrounding the first molding layer, the second molding layer, and the first solder bump. A portion of the third molding layer is between the first molding layer and the redistribution structure.
Public/Granted literature
- US20210082855A1 Chip Package Structure with Bump Public/Granted day:2021-03-18
Information query
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