A chip is described including a semiconductor layer including doped regions; a metallization layer on the semiconductor layer and at least one cell row including p-channel field effect transistors and n-channel field effect transistors, wherein the doped regions form source regions and drain regions of the p-channel field effect transistors and the n-channel field effect transistors; contacts extending from the source regions, the drain regions and gate regions of the p-channel field effect transistors and the n-channel field effect transistors to the metallization layer, wherein the metallization layer is structured in accordance with a metallization grid such that the p-channel field effect transistors and the n-channel field effect transistors are connected to form one or more logic gates.