An integrated circuit including a set of security modules configured to implement an asymmetric cryptography operation, the set of modules including a conditional exchange module configured to exchange first and second vectors used to manipulate input bits of a secret key, the conditional exchange module being suitable for applying an exchange formula including a combination of a condition of the input bit with the first and second vectors so that the latter are interchanged only if the condition of the input bit is equal to ‘1’, the conditional exchange module including a masking module suitable for making use of at least one random number to mask said exchange formula before it is applied.