Invention Grant
- Patent Title: Preemptive page fault handling
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Application No.: US16354859Application Date: 2019-03-15
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Publication No.: US11416411B2Publication Date: 2022-08-16
- Inventor: Murali Ramadoss , Vikranth Vemulapalli , Niran Cooray , William B. Sadler , Jonathan D. Pearce , Marian Alin Petre , Ben Ashbaugh , Elmoustapha Ould-Ahmed-Vall , Nicolas Galoppo Von Borries , Altug Koker , Aravindh Anantaraman , Subramaniam Maiyuran , Varghese George , Sungye Kim , Valentin Andrei
- Applicant: Intel Corporation
- Applicant Address: US CA Santa Clara
- Assignee: Intel Corporation
- Current Assignee: Intel Corporation
- Current Assignee Address: US CA Santa Clara
- Agency: Jaffery Watson Mendonsa & Hamilton LLP
- Main IPC: G06F12/1009
- IPC: G06F12/1009 ; G06N20/00 ; G06T1/20

Abstract:
Methods and apparatus relating to predictive page fault handling. In an example, an apparatus comprises a processor to receive a virtual address that triggered a page fault for a compute process, check a virtual memory space for a virtual memory allocation for the compute process that triggered the page fault and manage the page fault according to one of a first protocol in response to a determination that the virtual address that triggered the page fault is a last page in the virtual memory allocation for the compute process, or a second protocol in response to a determination that the virtual address that triggered the page fault is not a last page in the virtual memory allocation for the compute process. Other embodiments are also disclosed and claimed.
Public/Granted literature
- US20200293456A1 PREEMPTIVE PAGE FAULT HANDLING Public/Granted day:2020-09-17
Information query
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