Invention Grant
- Patent Title: Method and system for generating parity check matrix for low-density parity check codes
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Application No.: US16834310Application Date: 2020-03-30
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Publication No.: US11418216B2Publication Date: 2022-08-16
- Inventor: Shriharsha Koila , Aman Priyadarshi
- Applicant: Smart IOPS, Inc.
- Applicant Address: US CA Milpitas
- Assignee: Smart IOPS, Inc.
- Current Assignee: Smart IOPS, Inc.
- Current Assignee Address: US CA Milpitas
- Agency: Chip Law Group
- Main IPC: H03M13/11
- IPC: H03M13/11 ; G06F17/16 ; H03M13/03

Abstract:
A system for generating a parity check matrix for low-density parity-check (LDPC) codes includes a memory and a processing circuitry that retrieves a base matrix from the memory. The base matrix represents sets of valid and invalid positions for a set of circulant matrices. The processing circuitry determines a value for each valid position based on a heuristic function. The value for each valid position indicates a corresponding circulant matrix of the set of circulant matrices. The processing circuitry replaces each valid position with the corresponding circulant matrix based on the determined value, and each invalid position with a null matrix, to generate the parity check matrix. The parity check matrix thus generated has a high girth and equal distribution of cycles within the parity check matrix.
Public/Granted literature
- US20210306004A1 Method and System for Generating Parity Check Matrix for Low-Density Parity Check Codes Public/Granted day:2021-09-30
Information query
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